As field effect transistors have been scaled down to submicron levels, the hot-carrier effect has become a major concern. In N-channel devices, the hot-carrier effect occurs when drain region bias increases to the point where the transistor is operating beyond the saturation level. In this mode of operation, as electron carriers are accelerated from the source region through the channel region to the drain region, some attain sufficient kinetic energy to break silicon-to-silicon bonds within the channel region. As the silicon-to-silicon bonds break, hole/electron pairs are generated. The holes are attracted to the negatively-biased substrate, leading to a dramatic increase in substrate current. The free electrons, on the other hand, are attracted to the positively biased gate of the device. Although most of these free electrons manage to traverse the gate dielectric layer, some become trapped within the gate dielectric layer. Although the channel-to substrate and channel-to-gate current increases power dissipation in circuit, the trapping of electrons in the gate dielectric layer is far more serious, as the threshold voltage of the device is shifted upward and current drivability of the device is decreased. At some point, threshold voltage and drivability characteristics are degraded to levels which render the device unusable.
One of the most difficult tasks faced by a designer of a submicron field effect transistor is to improve hot-carrier lifetime of the device without degrading current drivability. As it is well known that the hot-carrier effect is exacerbated by a high lateral electric field strength in the channel region, a number of approaches have been taken over the past decade to reduce the maximum lateral electric field strength short channels. The double-diffused drain (DDD) structure, with its N- and N+ implants aligned to the same gate edge, allows little freedom in optimizing the length of the N- region. By introducing a sidewall spacer to offset the N+ implant from the gate edge, a lightly-doped drain (LDD) structure is formed which offers more freedom in setting N-region lengths. However, conventional LDD devices have certain disadvantages, such as "spacer-induced degradation", a second hump in the substrate current that is related to the N+ gate offset, and increased series resistance.
Certain modifications of the conventional LDD structure have been made in the interest of eliminating some of the aforementioned drawbacks. The fully-overlapped lightly-doped drain (FOLD) structure provides a reduction in peak electric fields in the channel region by having the gate electrode completely overlap the lightly-doped drain region. Researchers from several companies have experimented with angled implants of the N- impurity (phosphorus is typically the impurity of choice) in order to achieve FOLD-type structures. Although electric field strength is reduced by such a structure, the problem of elevated series resistance remains, thus limiting the speed of the device. What is needed is a new structure which not only reduces electric field strength in the channel region, but also reduces series resistance.